The present invention relates to a method for making twin tub integrated devices, in particular twin tub CMOS devices.
To manufacture advanced twin tub CMOS devices on almost intrinsic substrates with the known methods, starting from lightly doped, at the limit intrinsic, substrates two tubs are formed with opposite conductivity type (P and N) in which N and P-channel transistors are respectively formed. In order to reduce latch-up problems (that is, switching on of parasite SCR structures) and to obtain more compact circuits, the two doping tubs are separated by a trench, consisting of a digging in the silicon substrate obtained by means of a suitable mask and unidirectional physicalchemical etching of the silicon (reactive ion etching R.I.E.). Subsequently this trench is filled with insulating material by chemical vapor-phase deposition (CVD) of oxide or polysilicon, followed by the planarization of the structure.
A typical process sequence, according to the prior art, comprises the steps of: growing an initial oxide on a semiconductor substrate, deposition of the trench mask, oxide etching and silicon etching to form the trench, oxidation of the trench walls; deposition of polysilicon for filling the trench; planarization of the obtained structure; deposition of the P-tub mask and boron implant; deposition of the N-tub mask and phosphorus implant; diffusion of the two tubs; removal of the surface oxide and deposition of oxide and nitride layers; and the usual steps for the formation of CMOS devices.
This known method has several variations, with the tubs formed before opening the trench, with other methods for filling said trench and with other protection layers. However all these variated embodiments have in common the use of distinct masking steps for forming the masks for the N and P tubs, and for the trench.